The market for electronic apparatus and systems is driving industry to higher operating speeds for processors and enhanced memory capacity in the devices operating with such processors. Concurrent with this enhanced functionality is enhanced complexity and consumption of power. As memory capacity increases, so does the chance of storage or recall.
A number of configurations in computer memory exist to protect data against memory device failure. Error correction schemes, such as the Chipkill™ memory architecture, exist to protect computer memory systems from single memory chip failure as well as multi-bit errors from any portion of a single memory chip. In the Chipkill™ architecture, bits of multiple words of error correction code (ECC) data are scattered across multiple memory chips, such that the failure of any one memory chip will affect each ECC value so as to resemble the occurrence of multiple correctable errors. This configuration allows memory contents to be reconstructed despite the complete failure of one chip. More complex error correction schemes are seldom implemented, because additional memory and chip area are required.